Senior Validation and Verification Engineer
3 weeks ago
As a Senior Verification Engineer, you will be responsible for deploying advanced verification methodologies like UVM and Formal Verification in a fully remote capacity across the UK. Your key responsibilities will include developing and maintaining testbenches, UVCs, C models, and reusable verification environments for SoC projects. You will also be writing SystemVerilog assertions and performing coverage analysis, building frameworks for regression testing, and running power-aware simulations (UPF). Additionally, you will be using Python/Perl scripting to enhance workflows and team efficiency.
Key Responsibilities:
- Developing and maintaining testbenches, UVCs, C models, and reusable verification environments for SoC projects.
- Writing SystemVerilog assertions and performing coverage analysis.
- Building frameworks for regression testing and running power-aware simulations (UPF).
- Using Python/Perl scripting to enhance workflows and team efficiency.
Requirements:
- Skilled in developing unit and subsystem-level test benches using SystemVerilog/UVM.
- Experience in constrained random and metrics-driven verification.
- Expertise in AMBA protocols, bus interconnect functional verification, formal verification, and achieving coverage closure.
- Hands-on experience with Verilog, C/C++, SystemC, and scripting (TCL, Perl, shell).
- Strong analytical, communication, and collaboration skills.
What We Offer:
- A fully remote, UK-based position offering a daily rate of £300-£340.
- A great opportunity for an experienced Verification Engineer to work on leading-edge SoC projects while enjoying the flexibility of a remote working arrangement.
- Remote working/work at home options are available for this role.
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