Senior Verification and Validation Engineer
4 weeks ago
Contract Role: Senior Verification Engineer
Location: Fully Remote (UK)
Rate: £300-£340 per day (Daily Rate Contract)
Job Responsibilities:As a Senior Verification Engineer, you will deploy advanced verification methodologies like UVM (Universal Verification Methodology) and Formal Verification in a fully remote capacity across the UK.
You will be responsible for developing and maintaining testbenches, UVCs (Universal Verification Components), C models, and reusable verification environments for SoC projects.
Collaborating with design and systems engineers, you'll develop comprehensive test plans based on design documents, write SystemVerilog assertions, and perform coverage analysis.
You'll also build frameworks for regression testing, run power-aware simulations (UPF), and debug regression failures alongside cross-functional teams.
Automation is key, and you will use Python/Perl scripting to enhance workflows and team efficiency.
Requirements:- Verification Expertise: Skilled in developing unit and subsystem-level test benches using SystemVerilog/UVM, with experience in constrained random and metrics-driven verification.
- Protocol & Coverage Experience: Expertise in AMBA protocols, bus interconnect functional verification, formal verification, and achieving coverage closure.
- Technical Proficiency: Hands-on experience with Verilog, C/C++, SystemC, and scripting (TCL, Perl, shell).
- Soft Skills: Strong analytical, communication, and collaboration skills, with the ability to work in a dynamic, fast-paced, fully remote environment.
This is a fully remote, UK-based position offering a daily rate of £300-£340. It is a great opportunity for an experienced Verification Engineer to work on leading-edge SoC projects while enjoying the flexibility of a remote working arrangement.
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