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Senior Validation and Verification Expert
2 months ago
VanRath is seeking a highly skilled Senior Verification Engineer to join our team in a fully remote capacity. As a Senior Verification Engineer, you will be responsible for developing and maintaining testbenches, UVCs, C models, and reusable verification environments for SoC projects.
Key Responsibilities:
- Develop and maintain testbenches, UVCs, C models, and reusable verification environments for SoC projects.
- Collaborate with design and systems engineers to develop comprehensive test plans based on design documents.
- Write SystemVerilog assertions and perform coverage analysis.
- Build frameworks for regression testing and debug regression failures.
- Use Python/Perl scripting to enhance workflows and team efficiency.
Requirements:
- Expertise in developing unit and subsystem-level test benches using SystemVerilog/UVM.
- Experience in constrained random and metrics-driven verification.
- Protocol and coverage experience, including AMBA protocols and bus interconnect functional verification.
- Technical proficiency in Verilog, C/C++, SystemC, and scripting (TCL, Perl, shell).
- Strong analytical, communication, and collaboration skills.
This is a fully remote, UK-based position offering a daily rate of £300-£340. It is a great opportunity for an experienced Verification Engineer to work on leading-edge SoC projects while enjoying the flexibility of a remote working arrangement.
