Senior Testing Engineer M/F

1 month ago


United Kingdom Axelera Full time

ai , we are a pioneering semiconductor startup company in Europe, dedicated to pushing the boundaries of technology with a focus on multi-core in-memory compute SoCs. As a member of our physical design team, you will play a pivotal role in contributing to our ongoing success and innovation.
We offer a flexible, hybrid arrangement and, if needed, international relocation support, to work from one of Axelera AI offices in the Netherlands, Italy or the UK.
As a Senior Silicon Physical Design Engineer at Axelera.ai , you will be a key player in our physical design team, responsible for the development of Axelera's cutting-edge multi-core in-memory compute SoCs. You will leverage your extensive expertise in ASIC Physical Design, from RTL to GDS, to create physical design partitions that meet the highest standards in the industry. Your hands-on approach will encompass synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR signoff, and formal verification. Experience: You have a minimum of 10 years of experience in Physical Design, including a proven track record of implementing designs from RTL to GDS.
Communication and Teamwork: You excel in communication and teamwork, contributing effectively to diverse and inclusive teams.
Design Process: Your expertise includes synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. EDA Tools: You have hands-on experience with EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
Clocking: You possess a proficient understanding of clock tree synthesis (CTS) and different clock-building techniques.
IP Integration: You have experience in IP integration, covering memories, IOs, embedded processors, double data rate, networking fabrics, and Analog IP.
Scripting: Proficiency in scripting languages such as Python, Tcl, or Perl.
Language Skills: Fluent in English, both in speaking and writing.
Expertise in chip top-level integration, I/O ring design, ESD, and latch-up methodologies.
Experience interfacing with packaging teams and conducting chip-package-board co-simulations.
Influence: The ability to influence tools, flows, and overall design methodology.
Semiconductor Knowledge: Understanding of semiconductor device physics and transistor characteristics.
Multi-Domain Design: Experience with multi-clock, multi-power-domain design.
Autonomous Work: Capable of working autonomously and planning and performing research tasks.
We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.
At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard.


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