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CPU Modelling Architect

1 week ago

Cambridge, Cambridgeshire, United Kingdom microTECH Global Ltd Full time
The role we are seeking to fill is for a senior Technical Expert with a profound background in workload modelling and CPU/NPU Architecture.
This expert will be a key member of a team at the forefront of CPU/NPU development. Responsibilities will include planning and implementing tool systems for architectural exploration and performance analysis. Additionally, the role involves driving software/hardware vertical integration and planning software/hardware co-optimization features for next-generation processors.
The ideal candidate should possess a strong understanding of CPU/NPU architecture and workload extraction, as well as a good grasp of compiler, binary analysis, and software/hardware co-optimization.

Key Responsibilities:
Engage in the investigation of cutting-edge, high-performance server CPU/NPU core and SOC architecture design, contributing vital data support for crucial decision-making processes.
Design and execute the implementation of relevant tool systems for the exploration of architecture and the analysis of performance.
Develop strategies for software/hardware co-optimization features and lead the integration of software and hardware components for the next generation processor.
Construct a non-intrusive, highly accurate system for characterizing and modelling complex workloads, ensuring precise workload representation.
Analyse and extract the distinctive features of real-world scenario workloads, delivering essential insights to our in-house chip development department.

Required:
Possess extensive industry experience in workload modelling and the development of CPU/NPU architecture.
Skilled in performance projection and architectural exploration using SoC simulators.
Proficient in the development of Slicing Tools.
Skilled in developing and utilizing performance simulators, including GEM5 (O3 model), Sniper, and others.
Proficient in benchmark analysis and characterization.
Knowledgeable in using QEMU and DynamoRIO (or x86 PIN).
Strong grasp of binary analysis, and software/hardware co-optimization techniques.