Power Analysis Engineer

4 days ago

Cambridge, Cambridgeshire, United Kingdom La Fosse Full time
Job Title: Power Analysis Engineer

La Fosse is seeking a highly skilled Power Analysis Engineer to join their team. As a Power Analysis Engineer, you will be responsible for analyzing and optimizing the power efficiency of SoC design features from early estimation to final product validation.

Key Responsibilities:

  • Analyze the power efficiency of SoC design features using innovative technologies, methodologies, and tools.
  • Develop and run RTL simulator and emulator based workloads to analyze the power of the hardware design.
  • Take pre-silicon design power measurements throughout the SoC development cycle from early modeling, RTL analysis, to in-depth timing annotated netlist analysis.
  • Collaborate with multiple teams from SoC Architecture, Performance Analysis, Microarchitecture Design, to Physical design to develop and analyze real software use-cases and the physical hardware.
  • Build relevant metrics along with visualization to demonstrate the hardware power signature and capabilities of the compute subsystems.
  • Review the quality and accuracy of data produced by the latest EDA power analysis tool flows.
  • Continuously innovate by improving the power analysis methodologies used by the team.

Requirements:

  • Skilled in performing power modeling or pre-silicon power analysis flows.
  • Experience with low power design features and techniques, including clock and power gating, voltage/frequency scaling, memory/logic retention.
  • Ability to understand and balance trade-offs between power, performance, and area.
  • Familiar with developing RTL using Verilog, System Verilog, or VHDL.
  • Knowledge of Physical Implementation flow from RTL through Synthesis, Place & Route to STA.

Nice to Have:

  • A background in development based processors based SoC system designs.
  • Development or analysis of CPU or Graphics benchmarks for PPA analysis.
  • Experience using tools for power analysis, power delivery and signoff. (e.g. PowerPro, PrimePower, Redhawk, etc)
  • Background in running simulation/emulation tools. (e.g. VCS, Questasim, Incisive, Veloce Strato, Palladium, Zebu, etc)
  • Good understanding of the concepts and tools related to synthesis, place & route, clock tree synthesis, constraint development, timing closure. (e.g. Innovus, Tempus, etc)

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