Power Analysis Specialist

1 month ago

Cambridge, Cambridgeshire, United Kingdom La Fosse Full time
Power Analysis Engineer

La Fosse is seeking a skilled Power Analysis Engineer to join their team. As a key member of the organization, you will play a crucial role in analyzing and optimizing the power efficiency of next-generation compute solutions.

Key Responsibilities:
  • Analyze the power efficiency of SoC design features from early estimation to final product validation.
  • Develop and run RTL simulator and emulator-based workloads to analyze the power of the hardware design.
  • Take pre-silicon design power measurements throughout the SoC development cycle from early modeling, RTL analysis, to in-depth timing-annotated netlist analysis.
  • Collaborate with multiple teams to develop and analyze real software use-cases and physical hardware.
  • Build relevant metrics and visualizations to demonstrate the hardware power signature and capabilities of the compute subsystems.
  • Review the quality and accuracy of data produced by the latest EDA power analysis tool flows.
  • Continuously innovate by improving the power analysis methodologies used by the team.
Requirements:
  • Skilled in performing power modeling or pre-silicon power analysis flows.
  • Experience with low-power design features and techniques, including clock and power gating, voltage/frequency scaling, memory/logic retention.
  • Ability to understand and balance trade-offs between power, performance, and area.
  • Familiar with developing RTL using Verilog, System Verilog, or VHDL.
  • Knowledge of Physical Implementation flow from RTL through Synthesis, Place & Route to STA.
Nice to Have:
  • A background in development-based processors-based SoC system designs.
  • Development or analysis of CPU or Graphics benchmarks for PPA analysis.
  • Experience using tools for power analysis, power delivery, and signoff.
  • Background in running simulation/emulation tools.
  • Good understanding of the concepts and tools related to synthesis, place & route, clock tree synthesis, constraint development, timing closure.

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