Engineering Manager

6 days ago


Cambridge, Cambridgeshire, United Kingdom Arm Limited Full time

Arm Limited is seeking a highly motivated and experienced Senior Verification/Validation Engineer to join our System IP team. In this role, you will be responsible for leading the verification of complex digital systems through all phases of the design and verification flow.

About the Role

The estimated salary for this position is around $125,000 per year, based on industry standards and location. You will have the opportunity to utilise your engineering skills to develop cutting-edge technology, directly influencing the efficiency and performance of systems deployed in millions of devices.

Responsibilities
  • Work closely with the RTL design team to develop comprehensive verification strategies
  • Create and review design verification documentation
  • Design and implement SystemVerilog/UVM based verification IP and testbenches
  • Improve existing testbenches to increase performance, quality, and efficiency
  • Test and debug Verilog RTL
  • Define and implement functional coverage as well as enhance the testbench to ensure coverage closure
  • Plan and track tasks to meet the targets at the planned time
  • Drive the execution to ensure the quality of the design work done along with on-time delivery
  • Couch and mentor junior engineers
Requirements
  • Substantial experience of RTL verification for complex IP products
  • Proficiency in a hardware verification language, preferably SystemVerilog / UVM
  • Experience of development of coverage-driven constrained random test environments
  • Experience producing specifications and documentation describing complex designs
  • Strong communication skills and ability to work well as part of a team

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