Senior Verification Engineer
14 hours ago
We are looking for a highly skilled Verification Engineer to join our team in Cambridge, UK. The ideal candidate will have strong verification experience with knowledge of SystemVerilog and UVM.
The salary for this role is £80,000 - £110,000 per annum, depending on experience.
About the RoleThis is a challenging opportunity for a seasoned Verification Engineer to take their career to the next level. The successful candidate will be responsible for designing and implementing verification environments for complex digital systems.
In this role, you will work closely with our team of experienced engineers to deliver high-quality results and meet project deadlines.
Responsibilities- Develop and maintain verification environments using SystemVerilog and UVM
- Design and implement testbenches for complex digital systems
- Collaborate with cross-functional teams to deliver projects on time
- Provide technical guidance and support to junior engineers
- 6+ years of experience in verification
- Knowledge of SystemVerilog and UVM
- System verification experience
- Strong communication and collaboration skills
- Competitive salary and benefits package
- Opportunities for career growth and professional development
- Collaborative and dynamic work environment
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