Rival AMS DV Engineer
1 week ago
Rival is seeking a highly skilled AMS DV Engineer to lead the design verification for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. This role will play a key part in reimagining silicon and disrupting high performance computing platforms with RiscV based chiplet designs.
Key Responsibilities- Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage.
- Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation.
- Scripting skills in perl/python are preferred.
- Extensive experience in AMS DV engineering.
- Strong knowledge of digital and analog design verification methodologies.
- Excellent communication and teamwork skills.
We offer a competitive salary range of $140,000 - $180,000 per annum, depending on experience. We also provide a comprehensive benefits package, including health insurance, retirement plan, and paid time off.
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