Senior Design Engineer

2 months ago

London, Greater London, United Kingdom Normal Computing Corporation Full time

Your Role in Our Mission:

At Normal Computing Corporation, we're pioneering a novel approach to thermodynamic computing, aimed at accelerating probabilistic AI workloads by embracing noise. Our work combines cutting-edge research on the physics of computing with a mission to deliver scalable, reliable silicon and systems that revolutionize AI.

Key Responsibilities:

  1. You will play a pivotal role in the entire development process of our silicon, from conceptualization to architecture to implementation to tape-out.
  2. Design and floorplan complex mixed-signal chips with analog, digital, and mixed-signal blocks, ensuring optimal performance and efficiency.
  3. Lead the physical implementation of digital and mixed-signal chips using Cadence tools, driving innovation and excellence in our design processes.
  4. Perform top-level chip signoff, including timing checks, power analysis, logical equivalence checking, EM/IR analysis, and design rule checking, ensuring our silicon meets the highest standards.
  5. Participate in the tape-out, bring-up, and testing of Normal Computing Corporation's silicon, driving our products to market.

What Makes You a Great Fit:

  1. Strong familiarity with analog-on-top and digital-on-top design flows for mixed-signal chips, enabling you to drive our silicon development forward.
  2. Proficiency with the Cadence suite of physical design tools, including Virtuoso, Genus, Innovus, Quartus, Tempus, and Voltus, allowing you to leverage industry-leading technology.
  3. Experience in scripting languages, including Python, Perl, and/or TCL, empowering you to automate and optimize our design processes.

Bonus Points for:

  1. Experience mentoring or managing junior engineers, helping to grow our team's expertise and capabilities.
  2. Experience with mixed-signal PLL design, enabling you to contribute to our silicon's performance and efficiency.
  3. Experience with foundries and foundry aggregators to help acquire, set up, and support PDKs, set up and perform LVS and DRC flows, and tape out a completed silicon product, driving our products to market.

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