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Lead Engineer for Physical ASIC Implementation

3 months ago


Cambridge, Cambridgeshire, United Kingdom imec Full time

Senior ASIC Physical Design Engineer

Role Overview

We are seeking a skilled Senior ASIC Physical Design Engineer to take charge of the comprehensive Cadence Innovus Place & Route process. Your responsibilities will encompass:

  • Establishing low power design methodologies (CPF)
  • Executing floorplanning and power grid architecture
  • Implementing detailed Timing Driven Placement strategies
  • Managing Clock Tree Synthesis tasks
  • Conducting Scan chain re-stitching activities
  • Finalizing Detailed Timing Driven Routing (including Signal Integrity)
  • Enhancing designs for setup timing
  • Resolving setup and hold timing violations
  • Performing sign-off extraction and timing assessments
  • Carrying out Physical verification processes (DRC, ERC, LVS, ANT)
  • Overseeing partitioning and sub-block SDC file management for hierarchical designs

Candidate Profile

  • Possess a Master’s Degree in Electronics
  • Bring at least 10 years of experience in physical implementation for advanced technology nodes
  • Demonstrate proficiency in power reduction strategies
  • Exhibit strong communication abilities and a capacity to collaborate in an international environment
  • Show enthusiasm for engaging with clients

About Us

Become part of a prominent nanotechnology research institution dedicated to innovation and advancement. We provide a diverse and supportive workplace where your contributions are greatly appreciated. Expect development opportunities and competitive remuneration as part of our commitment to your professional growth.