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Senior Design Verification Engineer
2 months ago
Job Title - DV Engineer
Contract - 6 Months
Location - UK, Remote
Job responsibilities:
- Deploying Verification Methodologies such as UVM and Formal Verification
- Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
- Test plan development based on Design documents and interaction with design/systems engineers
- Writing and debugging SystemVerilog assertions
- Analysing coverage data and working with Design teams to address coverage holes
- Develop/augment framework for running regressions
- Running/Debugging Power aware simulations (UPF)
- Debugging regression failures with design/Systems teams
- Python/Perl automation for improving workflows and team efficiency
- Supporting software and other teams with debug
- Documentation
Required Experience:
- Experience in design and verification on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies.
- Proficient in developing unit and subsystem level test benches using SV/UVM methodology.
- Constrained random and Metrics driven verification.
- Experienced with C model integration and scorebording
- FW code integration verification
- Experience with AMBA protocols and BUS interconnect functional and formal verification along with coverage closure.
- Experience with power aware verification and clock domain crossing verification.
- Experience with debugging test failures
- Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
- Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting
- Strong analytical skills and ability to work in a dynamic and fast paced team environment.
- Excellent communication skills
- 8-12 years of experience
