Physical Design Engineer
1 month ago
We are growing our talent pool for Physical Design Engineers.
This advert is for future opportunities with Sondrel. If you have experience as a Physical Design Engineer in the UK or Morocco and meet the below criteria click on the link to register your interest.
Purpose of role
The Senior Physical Designer is expected to work as part of a Physical implementation design team. Within the team the designer will have responsibility for block development from RTL to GDS and will be expected to be diligent their ownership of the responsibilities assigned to them.
Responsibilities
- The person should contribute to physical design projects with some guidance and have some ability to work independently.
- Should be capable pf solving problems of moderate complexity
- Applies judgment in interpreting results and conducting quantitative analysis.
- Will be engaged in maintaining a high quality in their work.
- Should be capable of interacting with the more experienced team members to resolve problems.
- At this level the Consultant should show ability in many tools or be an expert in one or two. Examples of which are: Synthesis, PnR, Formal verification, Custom layout techniques, Analog simulation, and Chip finishing.
- Should be able to contributes to technical white papers.
- May contribute to sales support as part of a team.
- Should be capable of maintaining accurate time keeping.
Should be self-disciplined in executing design tasks.
Qualifications
A degree/masters or PhD in either a relevant subject
Desirable
Masters or PhD in a related subject but with 2 years practicable experience
Skills & experience
Essential
- Good understanding and implementation of complete physical design flow in 7nm, 14nm, 16nm and hands on experience in timing report analysis, EDA tool knowledge essential with either Synopsys (e.g., design compiler, ICC, ICC2, ICV, Primetime etc) and / or Cadence (Genus, Innovus, Tempus, Voltus etc) flows
- Input skill set one or more of the following: PnR using either Synopsys ICC, Cadence EDI, Mentor Olympus, Synthesis using either Synopsys DC or Cadence RC, Experience of Formailty or Formalpro, Experience of Mentor Calibre or Synopsys IC Validator
- Serves as an independent individual contributor to technical project
- Demonstrates capability as a problem solver with an ability to work individually or as part of a team
- Evaluates issues and defines solutions as part of a team or takes the lead in solving the issue
- Broadens cross disciplinary knowledge through new assignments
- Develops and presents technical white papers
- Experience in physical design on nodes at 7nm and under is preferred.
- Floorplanning – Experience of working with RTL designers to produce manual block floorplans, or familiarity with using FusionCompiler to generate automatic floorplans
- Synthesis, placement (and optimisation), CTS and routing using FusionCompiler and/or Genus.
- Good knowledge of automating process using Make systems and proficiency in Tcl.
- Static Timing Analysis using Primetime including generation and application of timing ECOs
Desirable
- Ability to take secondments abroad for 3-6 months.
- Applies advanced knowledge of a single sub-function OR thorough knowledge of multiple sub-functions
- Tcl, Perl and/or Python
- Insertion of DFT structures using Tessent (alternatively Tetramax)
- Logical Equivalence checking (Formality preferred, alternatively Conformal)
- DRC/LVS signoff using ICValidator
- IR-drop analysis using Redhawk/Seascape
Attributes
Essential
- Self-organisation and ability to respond to changing priorities quickly
- Team player
- Ability to work under pressure
- Organisation and problem-solving skills
- Self-motivated
- Excellent attention to detail
- Able to work under own initiative
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