Formal Verification Engineer

3 weeks ago


Oxford, Oxfordshire, United Kingdom ConSol Partners Full time

ConSol Partners are urgently seeking a Formal Verification Engineer for a leading manufacturer of semiconductor storage systems based in Oxfordshire

Key Responsibilities:

  • Develop and apply formal verification strategies for NVMe and PCIe-based memory storage designs.
  • Build formal testbenches using industry-standard tools (e.g., JasperGold, OneSpin, etc.).
  • Collaborate with RTL design, simulation, and validation teams to define verification scope and close coverage.
  • Analyze specifications and develop assertions and properties to validate design behavior.
  • Identify corner cases and verify design correctness under all conditions using formal techniques.
  • Document formal verification plans, methodologies, and results.

Required Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 3+ years of experience in formal verification of hardware systems.
  • Strong hands-on experience with NVMe and PCIe protocols.
  • Proficiency in SystemVerilog assertions (SVA), and experience with formal tools (e.g., Cadence JasperGold, Synopsys VC Formal, Siemens OneSpin).
  • Solid understanding of digital design principles and RTL development.
  • Ability to work independently and as part of a cross-functional team.

Preferred Qualifications:

  • Japanese language proficiency (business level or higher) is a strong plus.
  • Experience in verification of memory subsystems or storage controllers.
  • Knowledge of other verification methodologies (UVM, constrained-random simulation, coverage-driven verification).
  • Familiarity with scripting languages such as Python, Perl, or Tcl.


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