FPGA Design Verification Engineer.

This role will require Weekly access to London offices

This role is working for one of the biggest Tech companies globally.

Description:

Have you ever built out FPGA verification infrastructure from scratch / Processes? - They need an RTL verification expert to build up a UVM system and implement RTL simulations for system-level functional verification of our FPGA designs. Ideally, this candidate would be proficient with Cadence Xcellium, as this is the tool they use.

Skills:

Job Title: Verification Engineer (FPGA)

Location: Hayes, UK

Rate/Salary: - GBP Daily

Job Type: Contract

Trading as TEKsystems. Allegis Group Limited, Maxis 2, Western Road, Bracknell, RG12 1RT, United Kingdom. No. 2876353. Allegis Group Limited operates as an Employment Business and Employment Agency as set out in the Conduct of Employment Agencies and Employment Businesses Regulations 2003. TEKsystems is a company within the Allegis Group network of companies (collectively referred to as "Allegis Group"). Aerotek, Aston Carter, EASi, Talentis Solutions, TEKsystems, Stamford Consultants and The Stamford Group are Allegis Group brands.