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![Avensys Consulting](https://media.trabajo.org/img/noimg.jpg)
Design Verification Engineer
2 months ago
About Us:
Avensys is a reputed global IT professional services company headquartered in Singapore. Our service spectrum includes enterprise solution consulting, business intelligence, business process automation and managed services. Given our decade of success, we have evolved to become one of the top trusted providers in Singapore and service a client base across banking and financial services, insurance, information technology, healthcare, retail and supply chain.
Job Location : Remote
Duration : 12 Months Contract
At least 5 years of experience in Verilog and/or System Verilog.
• Experience on IP/block level Test-bench bring up on SV UVM based platform.
At least 5 years of experience in of IP verification including delivering to metric targets.
Able to understand complex Design specification, derive features and test bench architectures from concept.
Familiarity with CAD/EDA tools for Design and Simulation.
Aptitude for clear communication of issues and progress
Working knowledge in scripting languages for verification environments
Strong background in Digital Logic Design and Verification.