PMU Design Verification Intern

2 weeks ago

Swindon, Swindon, United Kingdom Apple Full time £40,000 - £80,000 per year

At Apple, we work every single day to craft products that enrich people's lives. The people here at Apple don't just build products - they create the kind of wonder that revolutionizes entire industries. We invite you to join our dynamic group, for the unique and rewarding opportunity to contribute to upcoming products that will delight and inspire millions of Apple's customers every day Apple's PMU Hardware Tech team are responsible for delivering the power in a highly configurable and controlled way to the high end Apple SoCs, which power everything from Apple Watch and Apple TV to iPhone, iPad and Mac. We're looking for dedicated students to help innovate the way we verify power management devices, to provide industry leading power and battery efficiency and achieve customer expectations of device performance. Do you love working on challenges that no one has solved yet? Then we welcome you to work among the industry's best As part of the Design Verification Team, you will assist with delivering high quality chips in order to meet performance, feature, timing, area, power and efficiency goals. We will provide you with the mentorship and the opportunity to collaborate with experienced Design Verification Engineers, as well as work alongside our Design, SoC Platform Architecture, and Physical Design teams. You will get the opportunity to be part of a team delivering PMU silicon directly into next generation Apple products and work with the state of the art verification techniques.

Description

Your tasks will include: - Develop your expertise in ASIC verification by working with a best-in-class Design Verification team to create verification plans, develop stimulus, define verification strategy and completeness metrics - Implement various components of the verification environment and participate in debugging test-bench code as well as deep design debug - Where applicable, run simulations with synthesized netlist and analyse/debug any issues encountered - Collaborate with the architecture and design teams to ensure any potential issues/critical cases are considered and dealt with as early as possible in the design cycle

Minimum Qualifications

  • Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field.
  • At the end of the internship, you must return to school to continue your education or the internship must be the last requirement for you to graduate.
  • Strong familiarity with understanding RTL design in Verilog/VHDL and logic structures being inferred Very good understanding of OOP basics and experience/exposure of using HDLs/HVLs such as SystemVerilog and/or UVM
  • Excellent interpersonal skills and well-organised working style
  • Strong analytical/problem solving skills
  • Ability to work well in a team and be productive under tight schedules

Preferred Qualifications

  • Knowledge of finite state machine, CPU bus architectures and mixed signal design/verification is desirable
    TCL/Perl/Python scripting experience/exposure

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