Senior Verification Engineer

Join to apply for the Senior Verification Engineer role at Siemens EDA (Siemens Digital Industries Software). We are Siemens EDA, a global technology leader in electronic design automation software. Our software tools enable companies worldwide to develop innovative electronic products faster and more cost‑effectively. Our embedded analytics technology powers systems‑on‑chips, allowing designers to add cybersecurity, functional safety and performance tuning features. What We’re Looking For Do you have expertise in silicon IP and digital design using RTL languages? Are you a verification engineer with experience of verifying silicon IP? We are looking for a highly capable and dedicated Digital Design or Verification Engineer to join our growing team at Tessent Embedded Analytics. If you can learn, grow, and succeed in this exciting position and relish the opportunity to shape the development of Tessent EA’s ground‑breaking silicon IP, we would love to meet you What You’ll Be Doing Verifying our IP from devising a verification plan through to coverage closure. Collaborating with design and architecture teams to understand design specifications and develop verification strategies. Accessing advanced tools and influencing the features of Mentor verification tools. Developing and executing detailed verification plans for ASIC designs, ensuring comprehensive coverage of all design features and functionalities. Creating and maintaining reusable, scalable, and robust testbenches using industry‑standard verification languages and methodologies (e.g., SystemVerilog, UVM). Identifying, analysing, and debugging design issues, working closely with design engineers to resolve them in a timely manner. Utilising and enhancing automated verification tools and scripts to improve efficiency and coverage. Mentoring and providing technical guidance to junior verification engineers, fostering a culture of continuous learning and improvement. Staying up‑to‑date with industry trends and advancements in verification methodologies and tools, integrating best practices into the verification process. What You’ll Bring Solid understanding of UVM and constraint‑random environments. Verification planning and management methods skills. Excellent SystemVerilog and Verilog experience, including experience of formulating and writing SystemVerilog coverage statements. Experience creating testbenches for and testing silicon IP. Experience using EDA simulation tools including Questa, VCS or Xcelium. Familiarity with metric‑driven verification methodology. The ability to work as part of a team and under pressure. Familiarity with other verification techniques such as formal and unit level testing. Nice if you have Familiarity with SVA assertions or similar. Familiarity with IC design and implementation. Experience in formal verification techniques and tools. Working at Siemens Software Flexibility is a norm: you can choose between working at home or the office at different times. We offer great benefits and rewards, as expected from a world leader in industrial software. Equal Opportunity Employment We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Siemens Industry Software is an equal‑opportunity employer and does not discriminate unlawfully on the grounds of age, disability, gender assignment, marriage, and civil partnership, pregnancy and maternity, race, religion or belief, sex, sexual orientation, or trade union membership. Seniority Level Mid‑Senior level. Employment Type Full‑time. Job Function Research. #J-18808-Ljbffr