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Verification Engineer
2 weeks ago
An experienced lead verification engineer who is a confident, motivated self-starter capable of independently driving complex work packagesBrings 10–20 years of industry experience in ASIC/FPGA hardware developmentA clear and articulate communicator who can collaborate effectively across cross-functional teams, time zones, and global locationsShows unwavering commitment to helping the team achieve high-quality results and meet development milestonesDriven to learn, grow, and perform at their highest technical capabilityEqually effective working independently or within a collaborative team environmentAble to quickly learn new concepts and independently acquire the skills needed for the roleKey Responsibilities:Provide technical leadership, guiding projects from initial requirements through final design verificationCollaborate with systems and hardware engineers to define high-level testbench architecturesEvaluate, adopt, and integrate new Adaptive SoC toolflows and methodologies into verification environmentsDevelop, modify, and maintain random and directed tests and associated libraries in SystemVerilog/UVMWrite, implement, and review detailed verification test plansParticipate in and conduct code reviewsTriage, analyse, and debug regression failuresPreferred Experience:Strong proficiency in advanced verification methodologies, including UVM, class-based testbenches, VIP integration, test plan creation, constrained-random testing, and coverage-driven sign-offExperience with high-speed connectivity protocols (e.g., 100Gb Ethernet, PCIe Gen5/Gen6, AMBA/AXI)Proficient in Python with solid understanding of build systems, regression frameworks, and CI/CD infrastructureExperienced with Git-based CI/CD workflowsSkilled in scripting languages such as TCL, Perl, and shellFamiliar with verification challenges specific to Adaptive SoCsUnderstanding of verification flows for complex embedded processor architectures (ARM, RISC-V, CPU)Knowledge of software flows in advanced SoCs, including embedded processor co-simulation and debuggingHands-on experience with adaptive SoC EDA tools (e.g., Vivado/Vitis)Academic Credentials:Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related discipline #J-18808-Ljbffr