Staff Performance Modelling Engineer

Overview In this role, your primary responsibility will be performance analysis of next-generation Interconnect IP. You will work closely with architecture, design, and modeling teams to evaluate design trade-offs, identify bottlenecks, improve modeling accuracy, and drive performance validation. About System IP This position is part of the Interconnect Product Team. The Interconnect team develops Arm's CoreLink Interconnect IP – scalable, high-performance NoCs designed for intelligent connected systems across markets such as mobile, IoT, networking infrastructure, and automotive. Our solutions are optimized for responsibilities. Responsibilities Drive performance analysis of Interconnect IP, including advanced Network-on-Chip designs. Evaluate architectural design trade-offs to influence performance and scalability. Investigate and identify performance bottlenecks through deep analysis and performance correlation against RTL emulation. Collaborate closely with architecture, RTL, and modeling teams to validate performance targets and provide actionable feedback. Contribute to C++-based performance models to support performance studies and system-level simulations. Build and extend infrastructure and tooling for insightful performance data visualization and analysis. Support system-level performance studies in collaboration with internal teams across Arm. Contribute to evolving performance analysis methodology and standard processes across Arm's System IP group. Qualifications Strong hands‑on experience in performance analysis and architectural performance tuning. Proficiency in C++ programming, particularly performance modeling and simulation. Solid understanding of computer architecture, particularly memory subsystems and interconnects. Python scripting experience for automation and data analysis. Nice‑to‑Have Skills and Experience Experience with SoC‑level performance analysis and tools. Familiarity with memory subsystem micro‑architecture and performance implications. Experience with Verilog/SystemVerilog RTL, including analysis and debugging in collaboration with design teams. Working knowledge of AMBA protocols and transaction-level modeling (SystemC/TLM). Exposure to Verilog/SystemVerilog and interaction with RTL design and verification teams. Experience mentoring other engineers in performance analysis or modeling efforts. Arm is committed to global talent acquisition, offering an attractive relocation package. With offices around the world, Arm is a diverse organisation of dedicated, creative and talented engineers. By enabling a dynamic, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their unrivaled contributions to Arm's success in the global marketplace. Our 10x mindset guides how we engineer, collaborate, and grow. Understand what it means and how to reflect 10x in your work: https://careers.arm.com/en/10x-mindset Accommodations at Arm: If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . All accommodation or adjustment requests will be treated with confidentiality. Hybrid Working at Arm: Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs. Equal Opportunities at Arm: Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. #J-18808-Ljbffr