Staff Engineer

Staff Engineer - CPU & ISA Architecture (Europe based) at Axelera AIAxelera AI is a deep‑tech startup building a next‑generation AI platform to advance humanity and improve the world. With over $120 million raised in four years, a global team of 220+ employees (49+ PhDs, 40,000+ citations) and offices in Belgium, France, Switzerland, Italy, the UK, and the Netherlands, we have launched the Metis™ AI Platform, delivering 3‑5× performance gains and a strong $100 million+ business pipeline.Position OverviewWe’re seeking an experienced R&D engineer specializing in CPU architecture. The ideal candidate has deep expertise in CPU design, analysis, and modeling, with a keen understanding of performance, power, and area (PPA) trade‑offs. Experience integrating architectural features into major ISAs (RISC‑V, ARM, x86) is highly advantageous. You will independently evaluate architectural proposals, develop innovative improvements, and prototype solutions to meet evolving AI training and HPC needs.Key ResponsibilitiesDesign & Analysis: Research, design, and evaluate CPU microarchitectural components (pipelines, fetch/decode, branch prediction, caches, memory hierarchy, OoO/rename/issue, interconnects, SIMD/vector/matrix units). Analyze and optimize PPA trade‑offs for AI, HPC, and cloud workloads.Modeling & Simulation: Build and validate performance/functional models, run simulations, and correlate results to RTL to guide architectural decisions.ISA Implementation: Develop and evaluate architectural extensions within RISC‑V; assess performance, programmability, and toolchain compatibility.Innovation & Prototyping: Propose, model, and prototype new mechanisms to improve efficiency, scalability, and performance.Collaboration & Research: Work closely with hardware, compiler, and system teams to align roadmaps and enable new capabilities. Stay ahead of trends in CPU, memory, interconnect, and AI‑adjacent architectures.QualificationsMS/PhD in CE/EE/CS (or related field) with focus on CPU architecture or microarchitecture.Deep expertise in CPU design, PPA optimization, and ISA extensions (RISC‑V, ARM, x86).Skilled in performance modeling and simulation (e.g., gem5, ChampSim, Sniper, QEMU), cycle‑accurate and trace‑driven analysis, and RTL correlation.Experience in benchmarking and workload characterization (SPEC, MLPerf, or internal suites).Proficient in RTL design and validation (Verilog/SystemVerilog/Chisel) with simulation, synthesis, and FPGA/emulation support.Knowledge of compiler/toolchain integration, low‑level software (C/C++/assembly), Linux kernel/driver development, and performance tuning for ISA features.Strong analytical, collaborative, and communication skills with proven ability to drive architectural proposals from concept to validation.Fluent in English.Able to work from one of our European offices or remotely, preferably based in Bavaria (Munich), Belgium, or Italy.Location & Working ArrangementWe offer flexible working arrangements:Work from one of our Axelera AI offices (Leuven, Belgium; Amsterdam, Eindhoven, Netherlands; Zurich, Switzerland; Florence, Milan, Italy; Bristol, UK) if you’re already based nearby.Work fully remotely from any European country (including the UK).Relocate with us and work from Italy (Florence or Milan), Belgium (Leuven), or the Netherlands (Amsterdam or Eindhoven).Priority will be given to candidates based in Bavaria (Munich), Belgium, or Italy.BenefitsCompetitive compensation package, pension plan, comprehensive employee insurances, and the option to receive company shares. An open culture that supports creativity, innovation, and collaborative ownership.Equal OpportunityAt Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. We welcome applicants from all backgrounds and are committed to fostering a warm, inclusive environment that empowers every team member to shape the future of AI. #J-18808-Ljbffr