Design Verification Manager

The candidate should meet the following requirementsJob DescriptionRole DescriptionThe ideal candidate will haveDesign Verification Manager Location: Cambridge (with a distributed European team)Company: Undisclosed – Semiconductors / Open HardwareType: Full-time, PermanentLevel: Senior ManagementAbout the Organisation:Our client is a highly respected engineering organisation operating at the forefront of silicon development. They specialise in delivering high-integrity digital IP, CPU architectures, and secure hardware components that are used by world-leading technology partners across industry and academia.With teams based across the UK and mainland Europe, this organisation has built a strong reputation for combining open, collaborative development models with best-practice ASIC/SoC design and verification methodologies. They run major multi-partner projects, contribute actively to the global open hardware ecosystem, and operate with a mission-driven, non-profit mindset that supports community, transparency, and long-term engineering excellence.This is an opportunity to join a genuinely unique organisation where your leadership will directly shape next-generation open-source silicon technology.The Role: Design Verification ManagerWe are seeking an experienced Design Verification Manager to lead and scale a multi-site team responsible for the verification of complex digital IP and SoC components.This is a senior technical leadership role with strong emphasis on:Team development and people management (remote based engineering team across EU)Strategic verification planningMethodology and process ownershipCross-functional coordination with design, architecture, and external project partnersOversight of distributed engineering teams across multiple time zonesAlthough the role is primarily managerial, there will be hands-on technical elements, particularly in customer-facing or architectural discussions.Key ResponsibilitiesTeam LeadershipLead, mentor, and develop a distributed team of Design Verification Engineers.Own hiring, performance reviews, coaching, and resource planning.Coordinate teams across multiple geographic sites and time zones.Verification Strategy & ExecutionDefine and own the overall verification strategy for digital blocks and full-chip integration.Ensure the team delivers high-quality verification aligned with project milestones.Methodology OwnershipOwn and continuously improve DV methodologies and flows (e.g., UVM).Champion best practices and scalable verification processes.Technical Guidance & LeadershipProvide technical direction and high-level oversight for DV activities.Ensure alignment with system architecture, design intent, and delivery timelines.Cross-functional & External CollaborationWork closely with design, architecture, software, and QA teams to ensure seamless verification.Collaborate with external stakeholders and customers; ensure technical requirements are met.Risk & Progress ManagementIdentify verification gaps or risks early.Track progress toward tape-out-quality sign-off.Ensure coverage completeness, quality metrics, and documentation standards.Required Skills & ExperienceStrong expertise in digital design and verification, including UVM and formal verification flows.Excellent SystemVerilog knowledge.Experience with scripting and DV automation, especially in Python.Skilled with advanced verification techniques such as constrained-random testing and coverage-driven verification.Demonstrated leadership experience; ideally has managed remote or multi-site teams.Strong communication and coordination skills, with ability to manage cross-functional engineering groups.Degree in Electrical Engineering, Computer Engineering, or relevant discipline (or equivalent experience).Why This Role Is AttractiveLead the DV strategy for industry-impacting silicon projects.Shape methodologies and build a scalable, multi-site European verification team.Work with a mission-driven organisation with long-term engineering values.Influence open standards and help define the future of open, secure hardware.