Formal Verification Engineer

6 days ago

London, United Kingdom IC Resources Full time

We are seeking a highly skilled and motivated Formal Verification Engineer to join our innovative and dynamic team. This role offers an exciting opportunity to work on cutting-edge formal verification projects for complex hardware designs, ensuring functional correctness, robustness, and quality before tape-out. If you are passionate about digital design, computer architecture, and problem-solving, we encourage you to apply. Mid to Staff level positions are being considered.As a Formal Verification Engineer, you will build cutting-edge formal verification testbench environments to find bugs and build proofs of bug absence in SoCs containing processors, video/GPUs, networking, AI/ML designs. You will play a critical role in developing and optimizing properties, executing advanced formal verification techniques, and collaborating closely with design teams to achieve verification closure. You will also have the opportunity to mentor junior engineers and contribute to the continuous improvement of our methodologies.ResponsibilitiesLead block/subsystem-level formal verification planning, define coverage goals, and contribute to verification strategiesAnalyse RTL specifications, derive corner-case scenarios, and demonstrate protocol expertise (e.g., AMBA, PCIe)Develop SystemVerilog Assertions (SVA) or PSL properties, constraints, covers, and abstraction techniquesApply advanced proof strategies, including induction, abstraction, and convergence improvementsAnalyse formal coverage metrics, identify unreachable code, and address coverage gapsProvide actionable debug guidance, root-cause analysis, and maintain strong cross-functional communicationQualificationsBachelor’s, Master’s, or Doctorate degree in Electrical/Electronic Engineering, Computer Science, Mathematics, or PhysicsTechnical Skills And Experience2-3 years of relevant design/verification experience including 1-2 years of formal verification experienceAt least one project where you independently managed small-scale formal verification tasks (less than 2 months)confident in Verilog/VHDL as well as fluent in SystemVerilog Assertions (SVA) and Tcl/Perl/Python and Unix/Linux scriptingSynopsys VC Formal, Cadence JasperGoldStrong analytical and mathematical skillsBenefitsWe offer a competitive compensation package aligned with prevailing market rates, along with a range of benefits.To apply, please contact Ane @ IC Resources with your CV and a time for a call.

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