Senior IC DFT Engineer

2 days ago

Cambridge, Cambridgeshire, United Kingdom EA First Full time
Job Title: Senior IC DFT Engineer

We are seeking a highly skilled Senior IC DFT Engineer to join our team at EA First in Cambridge. As a key member of our engineering team, you will be responsible for designing and implementing complex digital circuits for our cutting-edge technology solutions.

Key Responsibilities:
  1. Design and implement scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests, and pattern validation with and without timing.
  2. Perform DFT mode timing analysis and sign-off.
  3. Develop a comprehensive DFT plan and drive its implementation.
  4. Collaborate with cross-functional teams to achieve project goals.
  5. Train and mentor junior test engineers.
  6. Work with extended teams to develop project schedules and execute projects to completion.
  7. Generate, verify, and debug HDL and firmware-based test cases for DFT features of Flash-based FPGA.
  8. Improve, extend, and port existing DFT circuits and concepts to FPGA.
  9. Develop test benches and document test plans.
  10. Create and maintain comprehensive DFT documentation, requirements specifications, and test plans.
Requirements:
  1. Possess in-depth knowledge of analog and digital IC design principles.
  2. Experience with scan-stitching, MBIST/BISR implementation, and TestMAX ATPG and TestMAX DFT.
  3. Knowledgeable on test automation scripts, JTAG, I2C, I3C, and Spyglass debug and coverage co-relation.
  4. Experience with supporting ATPG and debug ATPG issues, MBIST/BISR insertion and debug insertion or verification issues, and gate-level simulations.
  5. Strong IC design and verification skills and relevant knowledge.
  6. Knowledge of EDA tools like Tessent, Cadence Module, or TestMax.
  7. Analytical thinking and attention to detail.
  8. Proficiency in using computer software and relevant tools.
  9. Highly skilled individual with many successful tape outs/experience.
  10. MBIST expert, ATPG/scan insertion expert, scan compression, JTAG, OCC, and function test generation.
  11. Very good vector generation and simulation skills.
  12. Experienced at interacting with external OSAT/test engineers.
  13. Industry knowledge of ATE test systems like Teradyne or Advantest.
Qualifications:
  1. An undergraduate degree or higher in engineering, physics, or a similar subject.

Location: Cambridge (Hybrid working possible)

Hours: Monday-Friday - Full-time

Salary: Excellent salary on offer

Benefits: 25 days annual leave, Private Health Insurance, Life Insurance, regular social/team events, travel opportunities, and more.

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