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Senior Physical Design Engineer
1 month ago
We are seeking a highly skilled Physical Design Engineer with expertise in Static Timing Analysis (STA) to join our client, a leading innovator in high-speed, energy-efficient chip-to-chip link solutions.
As a key member of the design team, you will be responsible for developing and validating timing constraints, conducting sign-off STA, and supporting timing closure at both block and full-chip levels.
Key Responsibilities:
- Developing and validating timing constraints, conducting sign-off Static Timing Analysis (STA), and supporting timing closure at both block and full-chip levels.
- Performing STA for both block and chip levels, working with the design team to review and define constraints, implementing SDC constraints for STA, analyzing timing violations, and resolving them with the frontend design and physical design (PD) teams.
- Contributing to the development of scripts, methodologies, and process improvements.
- Collaborating closely with the design team to meet STA requirements and implement effective solutions.
- Supporting IP and chip-level integration.
- Collaborating closely with the design team to meet STA requirements and implement effective solutions.
- Contributing to the development of scripts, methodologies, and process improvements.
- Performing STA for both block and chip levels, working with the design team to review and define constraints, implementing SDC constraints for STA, analyzing timing violations, and resolving them with the frontend design and physical design (PD) teams.
Requirements:
- Strong knowledge of RTL-to-GDS flow, including synthesis, place & route (P&R), logic equivalence checking (LEC), and STA.
- Self-driven, with a strong sense of ownership and responsibility. Excellent communication skills and a strong team player.
- Proficient in scripting languages (shell, TCL, Python, make) and experienced in data management (revision control systems).
- Experienced in gathering and defining SDC constraints, especially for top-level design, including DFT. Requires excellent teamwork, perseverance, attention to detail, and the ability to collaborate effectively with team members to gather information.
- Skilled in developing reusable workflows and processes across projects.
- 10+ years of experience in the semiconductor industry, with at least 5 years in a technical digital physical design role.
- Skilled in developing reusable workflows and processes across projects.
- Experienced in gathering and defining SDC constraints, especially for top-level design, including DFT. Requires excellent teamwork, perseverance, attention to detail, and the ability to collaborate effectively with team members to gather information.
- Proficient in scripting languages (shell, TCL, Python, make) and experienced in data management (revision control systems).
- Self-driven, with a strong sense of ownership and responsibility. Excellent communication skills and a strong team player.
About the Role:
This is a hybrid remote role, offering the flexibility to work from home and collaborate with the design team in Northampton, UK.
What We Offer:
Our client offers a competitive salary and benefits package, as well as opportunities for professional growth and development.
How to Apply:
If you are a motivated and experienced Physical Design Engineer with a passion for STA, please submit your application or contact us directly for more information.
