Staff Performance Analyst

4 weeks ago


Bristol, Bristol, United Kingdom CV-Library Full time
Performance Modeling Engineer Role

As a Performance Modeling Engineer at CV-Library, you will be responsible for creating system-level performance models to explore system architecture and configuration. This involves understanding new features, implementing them using performance models, evaluating their behavior, and working with system architects to improve their performance.

Key Responsibilities:

  • Engage with architects on future systems within Arm.
  • Create full system models using a range of IP models from across the company.
  • Run system performance characterization and optimization studies.
  • Develop exploration models for system components like Coherent/Non-Coherent interconnects, Last Level Caches (LLC/SLC), Dynamic memory controller (DDR5, LPDDR5/6, HBM etc).
  • Lead exploration studies aimed at determining the efficiency of proposed IP features in a system context.
  • Build infrastructure to enable better inspection and root-cause analysis of such systems.
  • Help define future direction of system performance modeling across Arm.

Requirements:

  • Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science with strong computer architecture, microarchitecture, performance experience.
  • Experience in developing and using cycle approximate/accurate performance models.
  • Experience in generating pre-silicon/pre-RTL performance projections and performance bottleneck debug and analysis.
  • Strong C/C++ programming and debugging skills.
  • Excellent interpersonal and communication skills.
  • Ability to work in teams and to collaborate with colleagues in other groups and sites.
  • Proactive and motivated.

Nice to Have:

  • Knowledge of on-chip bus protocols such as AMBA, coherency flows, interconnects, memory subsystems.
  • Knowledge of CPU microarchitecture.
  • Experience in evaluating/benchmarking system level performance using performance monitors.
  • Exposure to performance analysis and tuning in pre- and post-silicon environments.


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