Chip Design Optimization Specialist

1 day ago


Warrington, Warrington, United Kingdom ARM Full time
Key Responsibilities:
• Analyze the power efficiency of SoC design features from early estimation to final product validation.
• Develop and run RTL simulator and emulator-based workloads to analyze the power of the hardware design.
• Take pre-silicon design power measurements throughout the SoC development cycle from early modeling, RTL analysis, to in-depth timing-annotated netlist analysis.
• Collaborate with multiple teams to develop and analyze real software use-cases and the physical hardware.
• Build relevant metrics along with visualization to demonstrate the hardware power signature and capabilities of the compute subsystems.
• Review the quality and accuracy of data produced by the latest EDA power analysis tool flows.
• Continuously innovate by improving the power analysis methodologies used by the team.

• The salary for this position is estimated to be around $120,000 - $160,000 per year, depending on experience and qualifications.

This role requires a strong understanding of low-power design principles, power analysis tools, and methodologies. Experience with Verilog, SystemVerilog, or VHDL is highly desirable, as well as knowledge of physical implementation flow from RTL through Synthesis, Place & Route to STA.

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