Verification Engineer

3 weeks ago


London, Greater London, United Kingdom Apple Inc. Full time
About the Job

We are seeking a skilled Verification Engineer - Analog and Digital to join our team at Apple Inc. The successful candidate will be responsible for designing self-checking verification environments for multi-layer systems using the SystemVerilog UVM library.

About the Team

Our AMS DV team is focused on delivering high-quality verification environments and tests. We work closely with other engineers to ensure that our designs meet the highest standards of quality and performance.

Responsibilities:

  • Definition and design of self-checking verification environments
  • Collaboration with Analog and Digital Design engineers
  • Delivery of tests for design and test engineering teams

Requirements

  • Masters degree or PhD in Electrical/Computer Engineering or equivalent
  • Hands-on experience with System Verilog test-bench language and UVM library
  • Knowledge of Object Oriented Programming (OOP)

Compensation

The estimated salary for this position is $180,000 - $250,000 per year, depending on experience and qualifications.

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