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Formal Verification Specialist
2 months ago
Job Summary
Connected Consulting Limited is seeking a skilled Formal Verification Engineer to join our team. As a Formal Verification Engineer, you will be responsible for developing and maintaining formal verification environments for complex hardware IP designs.
Key Responsibilities:
- Review proposed design changes from a verification complexity perspective.
- Support the verification environment from investigation through to verification closure.
- Develop, maintain, and improve the SVA Formal testbenches.
- Develop, maintain and improve the suite of SVA Protocol Checkers for Formal and Simulation use.
Requirements:
- Proven experience of delivering formal verification environments for complex IP/module level designs.
- Property-based model-checking or Formal Property verification.
- Experience of writing assertions using SystemVerilog Assertions (SVA) using formal tools (e.g. Cadence, Mentor, Synopsys tools).
Nice to Have:
- Multiprocessing microarchitecture experience with knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
Working Arrangements:
Hybrid working arrangements are in place for this role, with 2 days onsite required each week. The role will also be classified as Inside IR35, working via an umbrella company.