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Principal ASIC Design and Verification Lead
2 months ago
We are seeking a highly experienced Principal ASIC Design and Verification Engineer to join our client's cutting-edge SoC team in the development of ASICs. The successful candidate will be working with experts in different aspects of SoC development on state-of-the-art projects.
Key Responsibilities- Mentor and guide engineers and peers in the design and verification process
- Collaborate with senior principal engineers to drive project success
- Develop and maintain expert-level understanding of the design and verification cycle
- Utilize leading-edge EDA tools and process nodes, with expertise in industry-standard languages and methodologies (e.g. SystemVerilog, UVM, Formal)
- Work on high-volume data centre and enterprise products used by industry-leading companies
- Experience working on projects with teams located internationally
- 15-20+ years of digital ASIC design and verification experience
- Vast experience in translating design requirements into RTL, deriving functional requirements for verification, and creating SystemVerilog UVM test benches
- Scripting languages and REST APIs (e.g. Perl, Python, TCL)
- Team player with excellent verbal and written communication skills
- Experience with Formal Verification (Jasper Gold or VC_Formal)
- Experience using SV UVM 1800.2
- Familiarity with C/C++
- Experience with storage interfaces: SAS, PCIe, NVMe (preferred) or SATA
- Competitive salaries ranging from £95,000 - £130,000 (depending on level and experience)
- 10%-20% bonus (based on company and individual performance)
- 25 days holiday + 8 days bank holiday per year
- 3 days a week on-site hybrid working
- Pension (matched group pension up to 8%)
- Life assurance
- Income protection
- Private medical
- Employee-supported volunteering
- Employee assistance program for health, wellbeing, financial services, legal services, etc.
- Training and development
- Visa sponsorship available
- Relocation support (if required)