Principal Digital Design Engineer

3 weeks ago

Edinburgh, Edinburgh, United Kingdom Renesas Electronics Full time
Job Description

Job Summary:

We are seeking an experienced Principal Digital Design Engineer to join our team at Renesas Electronics. As a key member of our data conversion and power management team, you will be responsible for architecting, designing, and integrating low-power digital circuits for mixed-signal power management products in advanced process nodes.

Key Responsibilities:

  • Interpret high-level requirements to design and integrate digital circuits that meet timing, area, and power specifications.
  • Support the full product lifecycle from concept to mass-production, communicating closely with the wider organization through various stages of silicon development.
  • Provide technical leadership and influence to the digital design team by contributing to technical discussions and reviews, mentoring junior engineers, and supporting recruitment.
  • Ensure the digital development process is state-of-the-art and achieves budget, schedule, and project deliverable goals.
  • Design digital RTL that meets timing, area, and power specifications.
  • Integrate design at the top level and run block and top-level simulations.
  • Participate in all aspects of mixed-signal design flow, including micro-architecture, design partitioning, RTL Verilog/SystemVerilog design, generating timing constraints, synthesis, interaction with P&R team, timing analysis, LINT, CDC, RDC, UPF.
  • Work closely with the P&R team to generate a layout that meets timing, area, and power requirements.
  • Support DFT strategy and implementation and review test case development.
  • Assist with top-level test-bench debug and run RTL and gate-level simulations.
  • Work with analog and digital verification engineers to come up with complex test scenarios for pre-silicon verification.
  • Support the analog team to develop AMS, SystemVerilog, or Verilog-real behavioral models.
  • Develop detailed block and chip-level design documents and collateral.
  • Hold and participate in key design reviews and completion of various checklists.
  • Document device errata, develop work-around solutions, and implement engineering changes when necessary.

Requirements:

  • More than 10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
  • Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
  • Fluent in Verilog/SystemVerilog RTL for digital CMOS circuit design.
  • Strong understanding of ASIC design methodology.
  • Strong understanding of Linting, CDC, and RDC tools.
  • Strong understanding of block-level and chip-level verification techniques.
  • Strong and proven ability to debug both RTL and gate-level simulations.
  • Experience with methodology and flow automation using appropriate scripting.
  • Experience with mixed-signal design methodologies.
  • Experience with developing design constraints and hand-off to P&R.
  • Experience with STA and timing closure.
  • Experience with low-power design techniques, including clock and power gating (UPF).
  • Experience with power analysis and optimization.
  • Experience with advanced verification methodologies (UVM).
  • Experience with industry-standard protocols (e.g., AMBA, I2C).
  • Mandatory competence in written and verbal English.

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