Senior Formal Verification Application Engineer
23 hours ago
Cadence Design Systems is a leader in electronic design automation, and we're looking for a talented Formal Verification Application Engineer to join our team.
About the Role
We're seeking a skilled engineer to work with our customers to deploy our market-leading Jasper Formal Verification products. As a key member of our Formal Verification Application Engineering team, you'll provide technical support, champion customer needs, and help drive innovation in formal verification technology.
Key Responsibilities
- Provide technical support for the deployment of Cadence's Jasper Formal Verification products
- Champion customer needs and help R&D develop competitive and creative technical solutions
- Deliver training courses for formal verification technology
- Lead projects and initiatives
Requirements
- BEng in Electronic / Micro-Electronic Engineering or Computer Science – or equivalent
- Experience of Hardware Design and Verification languages including PSL, SV Verilog, VHDL, System Verilog, System-C, TLM
- Experience with Unix/Linux environment including scripting languages
What We Offer
Cadence Design Systems offers a dynamic and collaborative work environment, with opportunities for professional growth and development. If you're passionate about formal verification and want to make a meaningful impact, we encourage you to apply for this exciting opportunity.
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