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Verification Specialist
2 months ago
Job Title: DV Engineer
Location: Remote
Job Type: Full Time Contract, 06 months
Work Model: Remote
Job responsibilities
• Developing and deploying verification methodologies, including UVM and formal verification.
• Creating test benches and verification components, such as UVCs, C models, and vertical/horizontal reusable verification environments.
• Developing test plans based on design documents and collaborating with design/systems engineers.
• Writing and debugging System Verilog assertions.
• Analyzing coverage data and working with design teams to address coverage holes.
• Developing and augmenting frameworks for running regressions.
• Running and debugging power-aware simulations (UPF).
• Debugging regression failures with design/systems teams.
• Automating workflows and improving team efficiency using Python/Perl.
• Supporting software and other teams with debugging.
• Documenting processes and results.
Candidate requirements:
• Experience in design and verification of SoCs and SoC methodologies for verifying complex units on SoCs using industry-standard tools and technologies.
• Proficiency in developing unit and subsystem-level test benches using SV/UVM methodology.
• Constrained random and metrics-driven verification.
• Experience with C model integration and scoreboarding.
• Firmware code integration verification.
• Experience with AMBA protocols and bus interconnect functional and formal verification along with coverage closure.
• Experience with power-aware verification and clock domain crossing verification.
• Experience with debugging test failures.
• Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion-based and formal verification techniques with System Verilog.
• Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting.
• Strong analytical skills and ability to work in a dynamic and fast-paced team environment.
• Excellent communication skills.
• 8-12 years of experience.