Principal Verification Engineer for RTL and Physical Design
4 weeks ago
Arm's Productivity Engineering group is responsible for developing tools and solutions across the technology stack to support the active development of hardware and software teams.
We are seeking a Hardware Verification engineer to join our hardware methodology team.
In this role, you will take ownership of developing verification standards, flows, and automation in areas where RTL and Physical Implementation are most closely linked, for example, for domain crossings (clock, reset, power).
Your work will be reused across products from Soft IPs to SoCs. You will work with other RTL design, verification, and physical design engineers to deploy standardized solutions enabling our hardware engineering teams to be more efficient.
Responsibilities:- Develop verification techniques for RTL structures related to clock, reset, and power domain crossings.
- Deploy solutions in active projects.
- Provide clear documentation and communication.
- At least 3 years of experience across hardware verification or design.
- Understanding of power domains, clock domain crossings, clock and reset distribution, power simulation & optimization.
- Familiarity with EDA tools like Synopsys, Cadence, or Siemens EDA.
- Proven experience of hardware verification using Verilog/System Verilog.
- Programming/scripting using Python, C++, TCL, or other relevant programming languages.
- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
- Familiarity with physical design flows and static design checks.
- Experience with Arm-based designs and/or Arm architectures.
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Principal RTL Verification Engineer
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