IP Design Engineer

3 weeks ago

South East London, United Kingdom Adroit People Ltd Full time

Greetings, We are hiring for a Senior IP Design Engineer Position in Cambridge OR London OR Milton Keynes, UK DOE The candidates resume must highlight relevant Adaptive SoC, FPGA, and protocol experience. Scope of Work The selected engineer will work closely with internal architecture, RTL, verification, and integration teams to design, implement, and optimize IP targeting AMD Adaptive SoCs. Responsibilities include: Developing RTL in SystemVerilog for high-performance FPGA/Adaptive SoC designs Implementing and optimizing high-speed connectivity protocols Collaborating with cross-functional teams on integration, timing closure, and validation Driving improvements across synthesis, place and route, and timing flows Supporting CI/CD development workflows using Git and scripting automatio Required Skills & Experience The proposed candidate must meet the following qualifications: A. RTL Design & Coding Deep hands-on experience with SystemVerilog HDL for RTL design Proven ability to develop IP targeting FPGA / Adaptive SoC platforms B. High-Speed Protocols Strong experience with: 100Gb Ethernet PCIe Gen5 AMBA/AXI interface protocols C. Adaptive SoC / FPGA Expertise In-depth understanding of FPGA/Adaptive SoC development flows, including: Synthesis Place and route Timing analysis and closure D. AMD Toolchain Experience Hands-on experience with AMD Vivado/Vitis tools and associated flows E. Scripting & Automation Proficiency in scripting: Python , Tcl Able to automate design, build, and verification workflows Comfortable with Git for CI/CD integration Deliverables RTL IP blocks developed in SystemVerilog according to project spec Timing-closed design implementations for target Adaptive SoCs Documentation for IP integration and usage Scripts and automation to support CI/CD workflows Weekly status updates and participation in technical reviews

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