Principal Digital If Fpga Engineer

I’m working on behalf of a worldwide specialist in RF Design and manufacturing. They design and build elements for satellite communications infrastructure.

You will be part of a small team within their engineering department, to specify, develop and design a new range of cutting edge digital IF distribution products.

**Role**

The role will suit someone with a strong background in network protocols and a working knowledge of communications systems engineering and digital signal processing. You may have worked in software radio or related discipline. A pragmatic approach to theimplementation of FPGA-based network equipment is essential. Ideally, you will have worked with SoC FPGAs such as Zynq or Cyclone device families.

You will be responsible for implementing VITA-49 or similar network SDR transport protocols. You will have excellent FPGA skills, including working on mid-sized to large designs where there are multiple code authors. Operating in a cloud CI environment.You will take sampled signals, process them, efficiently packetise and add context for data transmission over high-speed Ethernet. You will be able to size FPGA processing requirements and have a working knowledge of the benefits of leading FPGA devices.

You will be working on cutting-edge technology as part of a multidisciplinary team in a fast-paced environment. You will rapidly gain skills in all technologies present in a complex digitisation product line, working on some of the most complex and powerfulFPGAs on the market today.

**Key Responsibilities**
- To design and develop a range of modules and equipment for digital IF
- Integration and test of digital IF equipment
- Produce HDL code for VITA-49 or similar network SDR transport protocols
- Ability to write & debug Linux drivers
- Expert user of Linux
- Scripting in TCL designs utilising IP Cores for rapid development
- Build scripting to support continuous integration
- Design and development of test benches to prove VHDL code
- Conduct floor-planning and timing analysis of designs, achieving timing closure
- Test of VHDL code on target platform

**Essential Experience**
- Minimum of 8 years industry experience (or less with direct experience of RFSOC / M PSOC
- Experience of FPGA implementation of communications stacks including TCP/IP
- Extensive experience of FPGA synthesis tools such as Synplify, Vivado, Quartus or Mentor
- Extensive experience of writing FPGA test benches
- Efficient implementation of DSP algorithms in VHDL
- FPGA code design, synthesis, implementation and test
- Linux system configuration
- Experience in C / C++ / Rust or other high-level language

**Desirable Experience**
- Experience of SDR protocols such as VITA-49
- Understanding of data-converter specifications and error sources
- Experience of high-speed mixed signal PCB design constraints
- Build scripting for reproducible builds in a team environment
- Experience of working in an Agile Test-Driven environment