Verification Sv/uvm
1 month ago
Title/Position: Verification SV/UVM for TC48x NVM
Bristol or Munich.
SL.NO: I2
Key Responsibilities:
1) Develop testbenches for a non-volatile memory IP
2) Creation of agents
3) Make adaptations to existing and create new tests for new features of the NVM IP
4) Show that the relevant tests are passing
5) Define verification coverage
6) Testbench Qualification using Certitude
7) Documentation of verification results
8) Proof that relevant tests are passing
9) Proof that verification coverage (structural and functional) is reached
10) Proof that the testbenches have the required quality
TSMC relevant-yes
Proven experience (>5 years) in Digital IP verification using System Verilog / UVM
About us:
Company providing End to End Solutions from Product Engineering, Software, Hardware,
Wireless, Automotive and Embedded Solutions.
Company offers a unique combination of pre-silicon and post-silicon expertise to provide an
efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees
worldwide,
It provides a one-stop-shop solution with full-fledged hardware and software
capabilities, including its advanced silicon and system testing labs. It offers a Turnkey
ASIC Solution, from design to packaged parts. We have a global presence with office locations in
the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan,
Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.
Company offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.
Schedule:
- Monday to Friday
**Experience**:
- Electrical Engineering: 1 year (preferred)
Ability to Commute:
- London (required)
Ability to Relocate:
- London: Relocate before starting work (required)
Reference ID: TSL01
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