Design Verification Engineer
6 days ago
We have had an exciting opportunity become available for a Digital Verification Engineer in the South East, United Kingdom.
Role: Digital Verification Engineer
Location: South East, United Kingdom
Duration: Permanent
Salary: Negotiable
About the company:
Our client is driving disruptive innovations to help build a better future.
With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, our client creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
Job Summary:
• Plan and manage their work to achieve high quality outcomes on schedule.
• Architect, design, and implement digital functions.
• Perform verification planning and execute both digital and AMS verification.
• Develop UVM based test benches and execute a metric-driven, constrained random methodology.
• Write timing constraints and execute synthesis.
• Execute ATPG and work with the test engineering team to bring up production scan vectors.
• Successfully communicate with designers of multiple product types to deliver first-pass success silicon.
Requirements:
• MSEE, PhD preferred.
• 3+ years of professional experience.
• Proficiency in writing Verilog RTL and converging on a timing clean gate level implementation.
• Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
• Experience with UVM and System Verilog
• Ability to perform mixed mode verification.
• Must be a strong communicator in both verbal and written forms.
Required Skills:
UVM, System Verilog, OVM, C++, Python
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