SoC/ASIC Design Verification Engineer

1 month ago


United Kingdom zeroRISC inc. Full time

zeroRISC is committed to enabling trust in critical systems via transparently implemented security foundations. We embrace the use of open source technologies as a practical starting point for accessible, trustworthy, commercial engineering of secure systems. We contribute extensively to the OpenTitan open source silicon root of trust project and consider visibility a necessary precondition to building trust and reducing risk.

As a zeroRISC SoC/ASIC Design Verification Engineer, you will be responsible for developing, verifying, and maintaining security-centric chips. You will develop secure silicon, including root of trust technology, utilizing and contributing to open-source implementations. You will verify security ASICs including foundational system security, stability and safety. You will collaborate to help drive products through the full ASIC development lifecycle, from architecture through tapeout and silicon validation, with security as a primary design goal.

Minimum Qualifications
  • Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
  • 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools
  • Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments
Preferred Qualifications
  • Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
  • Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)
  • Knowledge of computer architecture and memory subsystem architectures
  • Experience verifying low power designs
  • Experience with scripting languages such as Python
Responsibilities
  • Execute full verification lifecycle from testplan definition through verification sign off including coverage closure and achieving passing regressions
  • Verify ASICs/SOCs at the chip/top and/or block levels, including functionality, performance, security, and power
  • Write high quality verification environments including engineering best practices
  • Write thorough verification documentation including test plans
  • Debug failures
  • Collaborate with architecture, design, software, system, and silicon validation teams to ensure design functionality through the whole development process
  • Collaborate with engineering program managers to effectively and efficiently deliver high quality, on schedule verification execution
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