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Design Verification Engineer

2 months ago

Cambridge, United Kingdom IC Resources Full time

GPU UK Division - Senior and Principal Verification Engineers


Like the look of this opportunity Make sure to apply fast, as a high volume of applications is expected Scroll down to read the complete job description.

Work on cutting edge designs within a prestigious group – Multiple UK Locations

I am seeking Senior and Principal level Verification Engineers to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP.

You will get the chance to work for a powerhouse whereby you will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products, and they are expanding their IP portfolio to include RISC-V CPUs as part of their efforts to create the best Compute offering in the market

You will:

  • Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off
  • Create verification plans, develop and maintain UVM testbench components
  • Participate in all stages of design specification definition providing feedback from the verification perspective
  • Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans.
  • Be responsible for the definition, effort estimation and tracking of your own work
  • Be able to influence and advance our GPU verification methodology
  • Have the opportunity to lead, coach and mentor other members of the team
  • Participate in design and verification reviews and recommend improvements

Qualifications

  • Have a proven track record of developing verification environments for complex RTL designs
  • Have excellent understanding of constrained-random verification methodology and challenges of verification closure
  • Be confident in defining verification requirements, and work out the implementation approach and details of a testbench
  • Be able to do root-cause analysis of complex issues and resolve them in a timely manner
  • Have excellent knowledge of SystemVerilog and UVM
  • Be able to develop new verification flows

You might also have:

  • Experience leading teams
  • Graphics/GPU/CPU/SoC knowledge
  • Experience in wider verification technologies, such formal property-based verification and code mutation

For more information and a confidential discussion on this superb opportunity contact Rachel Mason at IC Resources.