Design Verification Engineer
21 hours ago
Formal Verification Engineer - Cambridge (can do remote within the UK)
I am seeking a highly skilled and detail-oriented Formal Verification Engineer to join a dynamic start-up. The successful candidate will be responsible for applying formal methods to verify the correctness of hardware designs, ensuring that the systems meet functional specifications and are free of design errors. This position offers an exciting opportunity to work on cutting-edge technologies and contribute to the development of robust and reliable systems. With projects already in full flow and partnerships with some global names, this is a great opportunity for Juniors and Seniors alike to join
Key Responsibilities:
- Formal Verification of Hardware Designs:
- Use formal verification tools and techniques to verify digital designs at various levels of abstraction, including RTL and gate-level.
- Tool and Methodology Development:
- Develop, maintain, and enhance formal verification methodologies and scripts, as well as extend existing verification flows to improve efficiency and coverage.
- Testbench Creation:
- Create and maintain formal verification testbenches, ensuring comprehensive test coverage for complex designs and features.
- Bug Detection and Debugging:
- Identify design flaws, corner cases, and potential issues early in the design process using formal verification techniques. Provide in-depth analysis and support for debugging and fixing issues.
- Continuous Improvement:
- Stay current with advancements in formal verification techniques, tools, and best practices. Contribute to the development and adoption of new verification strategies to improve overall verification quality and efficiency.
Required Qualifications:
- Educational Background:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience:
- Proven experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools).
- Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL.
- Familiarity with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques.
- Experience with assertions (e.g., SVA - SystemVerilog Assertions) and formal verification environments.
On offer is the chance to join an early stage start-up with a founder who has already had previous success within the Semiconductor space. You will get equity and a competitive base salary. The role is open to Junior and Senior candidates.
You must have UK working rights to be considered for this role.
For more information, please contact Rachel Mason at IC Resources.
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