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Senior IP

2 months ago

Cambridge, United Kingdom ARM Full time
Job Description: 
 
Arm’s Systems Development team creates high performance and safety subsystems for various application segments, using the latest IP products from Arm and other vendors. We are looking for creative and enthusiastic SoC Verification Engineers to join the team to help verify these systems. 
 
Responsibilities: 
 
 As a verification engineer with a knowledge of subsystems and SoCs, you will be verifying functional correctness of compute subsystems. You will work with the project team to understand and review the subsystem architecture and design specifications, and to build a functional verification strategy. 
Your key responsibilities will include crafting test plans, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. You will also contribute to developing and improving the verification methodologies used by the team. In addition, you'll work closely with other teams on the design microarchitecture, verification methodologies, system performance, etc.  
You will balance other opportunities such as working with project management on activities, plans, and schedule as well as guide and support junior members of the team. 
 
Required Skills and Experience : 
5-10 year of experience on Automotive Functional Safety Verification 
Hands-on experience of HDLs such as or Verilog, SystemVerilog & coding test cases 
Experience in fault injection tools and methodologies (g. Z01X ) 
Experience in developing test cases from Safety Requirements 
Understanding of the fundamentals of processor architectures 
Coding with C/C++ language and assembly language, preferably Arm ISA, for functional coverage 
Analysing & reporting verification coverage to meet project delivery criteria’s 
Exposure to UVM or other industry standard verification methodologies 
“Nice To Have” Skills and Experience : 
Good knowledge and familiarity with ISO 26262 standard 
Understanding of Failure Mode Analysis and Safety Mechanisms 
Verification using Formal Verification and Hardware Emulation 
Experience on working on safety analysis like FMEA (Failure Modes and Effect Analysis), FTA (Fault Tree Analysis), DFA (Dependent Failure Analysis) as per ISO 26262 requirements. 
Experience of bringing up Fault injection methodology on emulator.
In Return:
 
We offer a competitive reward package including healthcare and wellness support. As well as other benefits such as a supplementary pension, and 25 days annual leave (with option to buy an additional 5 days per year) 
 
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