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Principal Engineer, Digital Physical Design

2 months ago

Scotland, United Kingdom Akkar Full time

Job Responsibilities:


  • Take full ownership of the Physical Design (PD) process at both block and chip levels.
  • Work with technologies ranging from 130nm BCD to 12nm FinFET, including advanced power management flows like UPF/CPF.
  • Lead the complete PD flow, encompassing synthesis, floor planning, place and route (P&R), static timing analysis (STA), IR and EM checks, and physical and power verification, including DRC and LVS.
  • Provide leadership in flow generation, collaborating closely with digital, DFT, and analog design teams.


Requirements:


  • Proficiency with Cadence place and route tools, as well as static timing analysers.
  • Strong understanding of timing requirements, clock tree synthesis, and DFT insertion techniques.
  • Experience with post-layout simulations and timing analysis.
  • Experience with physical verification (DRC/LVS) is a plus.