prin- analog mixed signal design verification engineer
1 week ago
Client:
Our client a leading a Multinational Semiconducto r Organisation requires Principal Analog Mixed Signal Design Engineer based in Edinburgh, Scotland or Sophia-Antipolis, France.
Role:
The candidate will join a team of Analog, Digital, Mixed-Signal CMOS designers, Mask Layout designers, Verification and Silicon Evaluation engineers, Algorithm and Software developers, Packaging and Production Test engineers, implementing PMIC state of the art.
The candidate will be involved in the following developments, from definition to production:
- LDO, BUCK, BOOST, BUCK-BOOST, CHARGE-PUMP, SIMO (Single-Input / Multiple Outputs)
- IBB (Inverted BUCK-BOOST), ICP (Inverted CHARGE-PUMP), Negative LDO
- Power Sequencer, Oscillators, PLL, Bandgap, References, ADC, DAC, I/O, SPI, I2C, SPMI, OTP, MTP, RAM, ROM, DFT
Responsibilities:
- Mixed-Signal Verification IP Development
- Improve AMS Verification Team Flows & Methodologies
- Bridge AMS / DMS Verification and Bench Evaluation environments
- Power Management IC Development
- Define and contribute to CSS products
- Integrate IPs, improve Integration Flows & Methodologies
- Execute on PMIC pre-silicon AMS verification and support PMIC post-silicon bench evaluation
- Execute for 100% PMIC verification coverage, combining DMS and AMS, Top-Level and IP-Level
- Technical Customer Interface Engagement
- Participate in customer engagements, in support of technical feasibility and proposals
- IC Development Weekly meetings / IC Milestone Workshops
- Human Resources Management
- Provide Mentorship and technical leadership, setting up framework and structure for efficient development flows
- Enable a culture of continuous learning and improvement
- Support project management and task planning
Education:
- Degree in Electrical Engineering, Computer Science, or Computer Engineering
Experience:
- 10+ years of experience
- IC AMS Verification Leading experience with multiple products introduced into the market
- Mixed-Signal Verification methodology and tools (AMS / APS / Flex)
- Good understanding of Mixed-Signal Design Flow and Top-Down development methodology
- Great technical and analytical background with good problem-solving skills
- Great team worker with multi-discipline, multi-cultural and multi-site environments
- Analog Functional and Parametric Verification
- Process - Voltage - Temperature (PVT) Corners, Layout Parameter Extraction (LPE) Simulations
- Analog Behavioral Models (Verilog-A, Verilog-AMS, Wreal, SystemVerilog, EEnet)
- Good written and verbal communication
Preferred Qualifications & Experience:
- Proficient with Cadence Suite (Virtuoso ADE Spectre)
- Scripting languages (Shell, TCL, PERL, Python)
- HDL programming languages (Verilog / SystemVerilog)
- Good understanding of Power IP Topologies
- Experience with Multiple Power and Clock domains
- IC Top-Level Digital UVM Environment Setup & Verification (Universal Verification Methodology)
- Verification Planning tools (ePlanner, vManager)
- Functional Oriented and Randomized Verification, Gate Level Simulation (GLS)
- Property Specification Language (PSL), SystemVerilog Assertions (SVA)
- Regressions and Coverage
- Lab silicon bring-up evaluation and Production Test support experiences
Contact:
For further information please contact Mícheál at Software Placements on or email
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